LOGICLAB: A COMPREHENSIVE WEB-BASED FRAMEWORK FOR DIGITAL LOGIC CIRCUIT VIRTUALIZATION AND REAL-TIME SIMULATION
DOI:
https://doi.org/10.5281/zenodo.17838254Keywords:
Digital Logic Simulation, Web-Based Virtualization, Sequential Circuits, Reactive Programming, Educational Technology, State Machines, Boolean Algebra, Circuit Visualization, Robotic Control SystemsAbstract
This thesis presents LogicLab, a web-based framework for virtualizing and simulating digital logic circuits in real time, spanning basic combinational logic through complex sequential circuits and finite state machines. The work targets limitations in existing digital logic education tools by delivering a zero-installation, multi-language platform that leverages modern reactive programming for immediate visual feedback and interactive learning, publicly available at logiclab.uz.
References
M. Morris Mano and Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th ed., Pearson, 2023.
Charles H. Roth Jr. and Larry Kinney, Fundamentals of Logic Design, 8th ed., Cengage, 2019.
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 3rd ed., Morgan Kaufmann, 2021.
Randy H. Katz and Gaetano Borriello, Contemporary Logic Design, 3rd ed., Pearson, 2014.
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 4th ed., McGraw-Hill, 2019.
A.Bainomugisha, A. Carreton, T. Van Cutsem, S. Mostinckx, and W. De Meuter, A Survey on Reactive Programming, ACM Computing Surveys, 45(4):52, 2013.
Robert Tarjan, Depth-First Search and Linear Graph Algorithms, SIAM Journal on Computing, 1(2):146–160, 1972.
Mentor Graphics, ModelSim Advanced Simulation User’s Manual, Siemens EDA, 2024.
IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description Language, IEEE, 2005.
IEEE Std 1076-2019, IEEE Standard VHDL Language Reference Manual, IEEE, 2019.
Frank Vahid and Roman Lysecky, Digital Design: An Embedded Systems Approach Using Verilog, 2nd ed., Elsevier, 2016.
